1. Field of the Invention
The present invention relates generally to the field of computer systems. More particularly, the present invention relates to the field of processing instructions having conditional program execution flow control.
2. Description of Related Art
Typical processors execute instructions out of order to help improve instruction throughput. Such processors typically process instructions through a pipeline that fetches instructions from memory, decodes each instruction, executes the instruction, and retires the instruction. The operation of each stage of the pipeline typically overlaps those of the other stages in time to help process instructions faster.
By identifying instructions that may be executed regardless of whether one or more prior fetched instructions are executed, typical processors may benefit from executing instructions in parallel, that is overlapping the execution of two or more instructions in time, and/or from executing instructions out of order to avoid stalling on any one instruction, for example, while waiting for the completed execution of an instruction upon which the stalled instruction depends. Instructions executed out of order are retired by the pipeline in order.
The pipeline generally fetches instructions of a program in a sequential order as defined by the program until the program alters its sequential flow with a jump or branch instruction, for example.
An unconditional branch instruction, for example, identifies a non-sequential target instruction that is to follow the unconditional branch instruction. The pipeline identifies the target instruction and then continues fetching instructions of the program starting with the target instruction. Before identifying the target instruction, however, the pipeline may have already fetched and started processing one or more instructions sequentially following the unconditional branch instruction as defined by the program. The alteration in the sequential flow of the program therefore penalizes the execution of the program as the pipeline is to flush such instruction(s) and restart fetching and processing at the target instruction. By identifying the target instruction early in the pipeline, such as in the fetch or decode stage for example, the pipeline helps avoid or minimize this penalty.
A conditional branch instruction identifies a non-sequential target instruction that is to follow the conditional branch instruction if a condition identified by the conditional branch instruction is satisfied. If the condition is not satisfied, the fall through instruction, that is the instruction sequentially following the conditional branch instruction as defined by the program, is to follow the conditional branch instruction. Because resolution of the condition relies on the execution of one or more other instructions, the condition may not be resolved when the conditional branch instruction is fetched. As the pipeline then cannot determine which instruction is to follow the conditional branch instruction, the pipeline typically predicts whether the target instruction or the fall through instruction will follow at the risk of penalizing the execution of the program if the pipeline later determines the wrong instruction was selected. If, for example, the pipeline selects the target instruction and the condition is not satisfied, execution of the program is penalized as the pipeline flushes the target instruction and any fetched instructions following the target instruction when the conditional branch instruction is retired and restarts fetching and processing at the fall through instruction.
The pipeline may try to predict how the condition will be resolved, for example, based on prior executions of the same conditional branch instruction in the program. Typical pipelines, however, cannot accurately predict how every conditional branch instruction will be resolved every time and will therefore incur execution penalties due to branch mispredictions.
Software predicated instructions, such as a conditional move instruction for example, may be used to eliminate or reduce branch instructions and therefore avoid or minimize execution penalties associated with branch mispredictions. Software predication, however, requires compiler help to substitute code in eliminating branch instructions and an instruction set architecture that provides for the software predicated instructions.